1. 9 Field of the Invention
This invention relates to testing electronic circuits at high operating speeds. More specifically, the invention relates to a method and device for testing of state machines using high speed clock signals.
2. Description of the Prior Art
It is well known that testing of electronic circuits at high operating speeds is difficult. In particular, testing at high speeds of high pin count application specific integrated circuits (ASICs) traditionally has required multi-million dollar tester equipment and man-months of test engineering for each design. As integrated circuits have achieved faster operating speeds over the years and include more input and output pins, testing such devices has become increasingly complex. To actually change the voltages, i e., input signals, on several hundred input terminal pins and then observe the output signals on several hundred other output terminal pins at high speeds is relatively difficult. Especially in the case of ASICs, which are typically produced in relatively small volume quantities, the engineering cost required to devise tests for such circuits at high speeds becomes prohibitive. Therefore in general such circuits are not tested at their rated speeds because to do so is beyond the capability of a particular tester or is inordinately expensive in terms of test engineering resources.
As is well known in the art, integrated circuits are typically subject to functional testing, in which input signals are provided to all of the input terminals of the integrated circuit and one observes the output signals on the output terminals in order to verify that the circuit is functioning as desired. One problem with the prior art is that functional testing for complex integrated circuits is typically carried out at an operating speed much lower than that at which the circuit is intended to operate in its particular application. Thus, an integrated circuit may pass the functional testing but not perform properly at its actual rated speed. For instance, the functional testing might occur at 10 mHz whereas the particular circuit has a rated speed of 30 mHz. Even though the integrated circuit passes the functional testing at 10 mHz, in the actual application by the user of the integrated circuit, the circuit might not function as desired at 30 mHz, because particular devices in the circuit may not operate at 30 mHz.
A typical case of a device on an integrated circuit which would pass the functional testing but not high speed testing is a transistor in the integrated circuit which is operating, but very weakly. Thus, for instance, instead of having an on-resistance of 2,000 ohms, as desired, it might have an on-resistance of 20,000 ohms. The circuit would then operate, but only at a much lower speed than was specified. Testing such circuits functionally at the higher operating speed requires changing all of the input signals, of which there might be 200 or more, at for instance the 30 mHz speed and then observing all of the output signals on the output pins, of which there again might be 200 or more. Each of the input and output signals would have to be observed to be in the correct desired state. This is a very expensive method due to the need to measure output pin states in an environment of capacitive and inductive coupling at high speeds. The electrical transients generated can easily cause good IC's to fail the test. Up to now the solution for at-speed testing has been custom "Device under Test" (DUT) boards and up to a man-year of fine tuning for testing each IC design.
Therefore, while functional testing of integrated circuits is relatively easy, testing of integrated circuits at their operating speed, often called "at speed" testing, is relatively difficult, expensive, time consuming and typically is not performed for application specific integrated circuits. This is undesirable because integrated circuits which do not meet their specific operating speed may be provided to circuit users. The defect in the circuits is only determined after they are installed in a user's system, causing significant expense.
It is well known in the art that logic circuits for digital systems may be combinational or sequential. A combinational circuit includes logic gates whose outputs at any time are determined directly from the present combination of input signals, without regard to previous input signals. Thus the outputs at any instant in time of a combinational circuit are entirely dependent upon the inputs present at that time. The second kind of logic circuit is a sequential circuit, which includes memory elements in addition to logic gates. The outputs of the logic gates are a function of the inputs and the state of the memory elements. The state of the memory elements, in turn, is a function of previous inputs. As a result, the output signals of a sequential circuit depend not only on the present inputs but also on past inputs, and therefore the circuit behavior is specified by a time sequence of inputs and internal states. The next state of the memory elements is also a function of external inputs in the present state. A sequential circuit, therefore, is a type of a state machine.
As also is well known in the art, an electronic clock is often used to control the timing of a digital system. Typically the output of a memory element is allowed to change states only when a pulse, i.e., a clock signal, is present and the speed of the system is fixed by the clock frequency. Because the clock signal synchronizes the timing, such systems are typically referred to as synchronous. Sequential networks in a digital system are typically synchronous.
As is well known in the art, conventional testing of integrated circuits that are state machines involves putting the circuit in state A, introducing some change ("test vectors") on one or more input terminal pins, then introducing a clock pulse to put the circuit in state B, observing state B, changing the input signals again to go to state C, observing state C, etc. This functional testing checks for each state of the signals on the output pins to determine if the circuit elements involved in each state transition are functioning correctly. Each state transition, if successfully accomplished, indicates that the certain elements or components involved in that state transition are functioning properly. Thus certain elements may be checked off on a list as being functional. This procedure is called fault grading. Ultimately, after having stepped through a large number of such state transitions, most individual devices, i.e., transistors, have been tested.